1. Field of the Invention
The present invention relates in general to an LVDS (Low Voltage Differential Signaling) receiver, and more particularly to an LVDS receiver that controls operating current based on its operating frequency.
2. Description of the Related Art
LVDS (Low Voltage Differential Signaling) is an industry standard that defines high-speed and low power data signaling techniques that are implemented in a variety of connection technologies. The LVDS is defined in ANSI/TIA/EIA-644. The LVDS provides high-speed data transmission with excellent noise immunity by means of differential signals having extremely low voltage levels, for example, 350 mV. Most importantly, the LVDS uses differential signaling for filtering out common mode noise.
The increasing data bandwidth necessary for communication and display applications, for example, has raised the importance of high-speed data signaling between chips, boards, and systems. Good EMI (Electromagnetic Interference) characteristics under a high operating frequency, as well as the strong noise immunity, make the LVDS suitable for such applications.
Because ANSI/TIA/EIA-644 does not specify protocols, connectors, or bus structures of the LVDS, application-specific specifications vary in accordance with the various applications.
Specifically, an application may use an LVDS interface that operates on an input signal with a wide ranging operating frequency. Usually, an LVDS input buffer is designed based on a maximum operating frequency, and thus excessive current is consumed while operating at the normal frequency.
In a display application, EMI characteristics and low power consumption are becoming more important as the resolution and color depth of the display increase. For example, for the display device for a notebook PC and a PDA (Personal Digital Assistants), minimizing the display's power consumption is a first consideration in determining competitiveness of the notebook PC and the PDA. Low power consumption is a key point for increasing battery life span for portable devices that use a limited capacity of batteries.
FIG. 1 is a block diagram illustrating a conventional data transmission between a graphics control unit and a timing control unit via LVDS.
For the sake of generalization, the graphics control unit 110 and the timing control unit 130 can be named differently and can exist as the sub part of any other main components or as any other mixed components.
Referring to FIG. 1, for this example, the graphics control unit 110 converts an analog video signal supplied from a RAMDAC (Random Access Memory Digital Analog Converter) to a digital video signal. In addition, the graphics control unit 110 transmits RGB (Red, Green, Blue) data signals generated from the received analog digital video signal to the timing control unit 130.
FIG. 1 illustrates when a conventional analog video interface is used. When a digital video interface such as DVI (Digital Video Interface) is used, analog-digital converting is not necessary and the function of the graphics control unit 110 may be slightly varied. Returning to the conventional analog video interface as described above, the digital video signal converted by an AD converter 111 is transmitted to the timing control unit 130 via a scaler 112 and an LVDS transmitter 1113.
In the timing control unit 130, an LVDS receiver 131 receives the digital video signal from the LVDS transmitter 1113 and provides a timing controller 132 for the digital video signal. The timing controller 132 provides a column driver and a row driver of an LCD panel 150 with the RGB data signal in response to HSYNC (Horizontal Synchronization) and/or VSYNC (Vertical Synchronization) signals via an RSDS (Reduced Swing Differential Signaling) transmitter 133.
Usually, the LVDS interface is used for the data transmission between the graphics control unit 110 and the timing control unit 130 and may operate on data signals with wide frequency ranges. Because various resolutions and color depths are supported by recent display devices, the data transmission rate of the LVDS interface needs to cover a wide frequency range.
As an example, a display device for a PC (Personal Computer) operates in VGA (Video Graphics Array) mode during a booting sequence, and operates in a display mode with a higher resolution and a color depth set by a user after the booting sequence ends. Moreover, the display mode with the higher resolution is selected when a specific application such as a game, is executed, and after the application the display device returns to the normal display mode. For example, a 25 MHz operation frequency corresponds to a VGA display mode, and a 135 MHz operation frequency to a SXGA (Super Extended Graphics Array) display mode. Therefore, the LVDS transmitter 113 and LVDS receiver 131 need flexibility according to the user's display setting and environmental requirements.
FIG. 2 is a detailed block diagram showing a conventional LVDS transmitter and a conventional LVDS receiver in the graphics control unit and the timing control unit of FIG. 1.
Referring to FIG. 2, the LVDS transmitter 113 and the LVDS receiver 131 may be implemented on different chips. Therefore, a plurality of transmitter chips and receiver chips may be used to implement the LVDS interface between the graphics control unit 110 and the timing control unit 130. For example, additional LVDS transmitters and LVDS receivers may be added in parallel to achieve required data bandwidth.
The LVDS transmitter 113 shown in FIG. 2 has four groups, each having seven channels, totalling twenty eight channels. A serializer 210 converts low speed parallel data of twenty eight channels to four high speed serial data streams. LVDS output buffers 212a, 212b, 212c, and 212d transmit serial data streams to the LVDS receiver 131. Thus, four LVDS output buffers 212a, 212b, 212c and 212d can handle four serial data streams.
A clock generating unit, for example a PLL (Phase Locked Loop)/DLL (Delay Locked Loop) 220, receives a clock signal of the LVDS transmitter 113 and supplies a suitable clock signal to the serializer 210 and LVDS output buffers 212a, 212b, 212c, and 212d. The clock generating unit may include a voltage controlled oscillator with an output frequency controlled by a control voltage. When the LVDS transmitter operating frequency is in a range from 25 MHz to 135 MHz, as mentioned above, the LVDS output buffer's operating frequency may be in a range from 87.5 MHz to 472.5 MHz: when NRZ (Non Return to Zero) coding is used for data transmission, the LVDS output buffer's operating frequency (87.5 MHz˜472.5 MHz) is three and half times the LVDS transmitter's operating frequency (25 MHz˜135 MHz).
Four LVDS input buffers 231a, 231b, 231c, and 231d receive the data transmitted by the LVDS output buffers 212a, 212b, 212c, and 212d of the LVDS transmitter 113. The operating frequency of the four LVDS input buffers 231a, 231b, 231c, and 231d is identical to that of the LVDS output buffers 212a, 212b, 212c, and 212d. A deserializer 230 converts the four high speed serial data streams received by the four LVDS input buffers 231a, 231b, 231c, and 231d to low speed parallel data of twenty eight channels. The LVDS receiver 131 also includes a clock generating unit 240, such as a PLL or a DLL, that may include a voltage controlled oscillator with an output frequency controlled by a control voltage.
The clock generating unit 220 in the LVDS transmitter 113 and the clock generating unit 240 in the LVDS receiver 131 may communicate with each other via clock output LVDS buffer 221 and clock input LVDS buffer 241 so that the clocks of the clock generating units 220 and 240 are synchronized with each other.
FIG. 3 is a circuit diagram illustrating a conventional rail-to-rail LVDS input buffer.
Referring to FIG. 3, an LVDS input buffer 300 has an N-type differential amplifier 310, a P-type differential amplifier 330, and a comparator 350. The differential amplifier 310 has a first current source 315, and the differential amplifier 330 has a second current source 335. Both the current sources 315 and 335 supply current to the differential amplifiers 310 and 330, respectively. As mentioned earlier, as the operating frequency of the LVDS input buffer 300 increases, the current supplied to both differential amplifiers 310 and 330 should increase. Thus, the first and second current sources 315 and 335 are designed to satisfy the maximum current corresponding to the maximum operating frequency. In this design scheme, when the LVDS input buffer 300 operates at a frequency lower than the maximum frequency, an unnecessarily excessive amount of current is supplied to the LVDS input buffer 300. In applications where a battery's life span is important, this excessive current may be a severe factor for reducing the battery life span.